Encoding:

Format:

MAQ_S[A].W.PHL 

MAQ_S.W.PHL  ac, rs, rt 

MAQ_SA.W.PHL ac, rs, rt

Purpose:

Multiply with Accumulate Single Vector Fractional Halfword Element

To multiply one pair of elements from two vectors of fractional halfword values using full-sized intermediate products and accumulate the result into the specified 64-bit accumulator, with optional saturating accumulation.

Description:

ac = sat32(ac + sat32(rs31..16 * rt31..16))

The left-most Q15 fractional halfword values from the two right-most paired halfword vectors in each of registers rt and rs are multiplied together, and the product left-shifted by one bit position to generate a Q31 fractional format intermediate result. If both multiplicands are equal to -1.0 in Q15 fractional format (0x8000 hexadecimal), the intermediate result is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal). The intermediate result is then sign-extended and accumulated into accumulator ac to generate a 64-bit Q32.31 fractional format result.

In the saturating accumulation variant of this instruction, if the accumulation of the intermediate product with the accumulator results in a value that cannot be represented as a Q31 fractional format value, the accumulator is saturated to either the maximum positive Q31 fractional format value (0x7FFFFFFF hexadecimal) or the minimum negative Q31 fractional format value (0x80000000), sign-extended to 64 bits.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If overflow or saturation occurs, a 1 is w ritten to one of bits 16 through 19 of the DSPControl register, within the

ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

MAQ_S.W.PHL:
   tempA31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
   tempB63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + ( (tempA31)32 || tempA31..0 )
   ( HI[ac]63..0 || LO[ac]63..0 )  = (tempB63)32 || tempB63..32 || (tempB31)32 || 
tempB31..0
MAQ_SA.W.PHL:
   tempA31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
   tempA31..0 = sat32AccumulateQ31( ac, temp )
   tempB63..0 = (tempA31)32 || tempA31..0
   ( HI[ac]63..0 || LO[ac]63..0 )  = (tempB63)32 || tempB63..32 || (tempB31)32 || 
tempB31..0
function sat32AccumulateQ31( acc1..0, a31..0 )
   signA = a31
   temp127..0 = HI[acc]63..0 || LO[acc]63..0
   temp127..0 = temp + ( (signA)96 || a31..0 )
   if ( temp32 != temp31 ) then
      if ( temp32 = 0 ) then
          temp31..0 = 0x80000000
      else
          temp31..0 = 0x7FFFFFFF
      endif
      DSPControlouflag:16+acc = 1
   endif
   return temp31..0
endfunction sat32AccumulateQ31

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The MAQ_SA version of the instruction is useful for compliance with some ITU speech processing codecs that require a 32-bit saturation after every multiply-accumulate operation.